The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

May. 30, 2018
Applicant:

Spin Transfer Technologies, Inc., Fremont, CA (US);

Inventors:

Pradeep Manandhar, Fremont, CA (US);

Prachi Shrivastava, Fremont, CA (US);

Mustafa Pinarbasi, Fremont, CA (US);

Thomas Boone, Fremont, CA (US);

Assignee:

Spin Memory, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/12 (2006.01); H01L 43/08 (2006.01); H01L 43/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); H01L 21/3065 (2013.01); H01L 21/31051 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01);
Abstract

A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.


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