The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Jan. 11, 2018
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Hans-Joachim Schulze, Taufkirchen, DE;
Jens Peter Konrath, Villach, AT;
Roland Rupp, Lauf, DE;
Christian Hecht, Buckenhof, DE;
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 21/04 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/0465 (2013.01); H01L 21/26506 (2013.01); H01L 21/762 (2013.01); H01L 21/76254 (2013.01); H01L 29/7395 (2013.01); H01L 29/7827 (2013.01);
Abstract
Representative implementations of devices and techniques provide an optimized layer for a semiconductor component. In an example, a doped portion of a wafer, forming a substrate layer may be transferred from the wafer to an acceptor, or handle wafer. A component layer may be applied to the substrate layer. The acceptor wafer is detached from the substrate layer. In some examples, further processing may be executed with regard to the substrate and/or component layers.