The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Oct. 19, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ming Zhu, Singapore, SG;

Pinghui Li, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Yiang Aun Nga, Singapore, SG;

Danny Pak-Chum Shum, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 27/1157 (2017.01); H01L 21/336 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/7851 (2013.01);
Abstract

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.


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