The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Apr. 25, 2018
Applicant:

Win Semiconductors Corp., Tao Yuan, TW;

Inventors:

Chang-Hwang Hua, Tao Yuan, TW;

Wen Chu, Tao Yuan, TW;

Assignee:

WIN SEMICONDUCTORS CORP., Tao Yuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 29/45 (2006.01); H01S 5/024 (2006.01); H01S 5/042 (2006.01); H01S 5/02 (2006.01); H01S 5/34 (2006.01); H01L 23/373 (2006.01); H01S 5/32 (2006.01); H01L 33/12 (2010.01); H01L 33/40 (2010.01); H01S 5/183 (2006.01); H01S 5/187 (2006.01); H01L 23/367 (2006.01); H01L 29/861 (2006.01); H01L 29/866 (2006.01); H01L 29/872 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/22 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/373 (2013.01); H01L 29/45 (2013.01); H01L 29/452 (2013.01); H01L 33/12 (2013.01); H01L 33/40 (2013.01); H01S 5/0206 (2013.01); H01S 5/02476 (2013.01); H01S 5/0425 (2013.01); H01S 5/3201 (2013.01); H01S 5/3406 (2013.01); H01L 23/367 (2013.01); H01L 29/1608 (2013.01); H01L 29/20 (2013.01); H01L 29/22 (2013.01); H01L 29/24 (2013.01); H01L 29/861 (2013.01); H01L 29/866 (2013.01); H01L 29/872 (2013.01); H01L 2933/0016 (2013.01); H01S 5/187 (2013.01); H01S 5/18311 (2013.01); H01S 5/18344 (2013.01); H01S 2301/173 (2013.01);
Abstract

An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.


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