The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Dec. 26, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vyom Sharma, Portland, OR (US);

Rohan K. Bambery, Hillsboro, OR (US);

Christopher P. Auth, Portland, OR (US);

Szuya S. Liao, Hillsboro, OR (US);

Gaurav Thareja, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28132 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/4983 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01);
Abstract

An embodiment includes a system comprising: a first gate and a first contact that correspond to a transistor and are on a first fin; a second gate and a second contact that correspond to a transistor and are on a second fin; an interlayer dielectric (ILD) collinear with and between the first and second contacts; wherein (a) the first and second gates are collinear and the first and second contacts are collinear; (b) the ILD includes a recess that comprises a cap layer including at least one of an oxide and a nitride. Other embodiments are described herein.


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