The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

May. 23, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sungwoo Kim, Hwaseong-si, KR;

Bong-Soo Kim, Yongin-si, KR;

Youngbae Kim, Seoul, KR;

Kijae Hur, Seoul, KR;

Gwanhyeob Koh, Seoul, KR;

Hyeongsun Hong, Seongnam-si, KR;

Yoosang Hwang, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); G11C 14/00 (2006.01); H01L 27/24 (2006.01); H01L 23/528 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01); G11C 11/00 (2006.01); G11C 5/02 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0045 (2013.01); G11C 5/025 (2013.01); G11C 11/005 (2013.01); G11C 13/0004 (2013.01); H01L 23/528 (2013.01); H01L 27/2427 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); G11C 13/0007 (2013.01); G11C 2213/15 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/52 (2013.01); G11C 2213/76 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10897 (2013.01); H01L 45/1253 (2013.01); H01L 45/143 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.


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