The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Jun. 30, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Patrick P. Lai, Fremont, CA (US);

Ethan Schuchman, Santa Clara, CA (US);

David Keppel, Mountain View, CA (US);

Denis M. Khartikov, San Jose, CA (US);

Polychronis Xekalakis, San Jose, CA (US);

Joshua B. Fryman, Corvallis, OR (US);

Allan D. Knies, Burlingame, CA (US);

Naveen Neelakantam, Mountain View, CA (US);

Gregor Stellpflug, Braunschweig, DE;

John H. Kelm, Sunnyvale, CA (US);

Mirem Hyuseinova Seidahmedova, Barcelona, ES;

Demos Pavlou, Barcelona, ES;

Jaroslaw Topp, Schoeppenstedt, DE;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 15/76 (2013.01); G06F 9/30174 (2013.01); G06F 9/3824 (2013.01); G06F 9/3832 (2013.01); G06F 9/4552 (2013.01); G06F 9/46 (2013.01);
Abstract

Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.


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