The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Oct. 06, 2017
Applicant:

Utac Headquarters Pte. Ltd., Singapore, SG;

Inventors:

Yongbo Yang, Singapore, SG;

Antonio Jr. Bambalan Dimaano, Singapore, SG;

Chun Hong Wo, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/27 (2013.01); H01L 21/486 (2013.01); H01L 21/4846 (2013.01); H01L 21/6835 (2013.01); H01L 21/76885 (2013.01); H01L 23/3128 (2013.01); H01L 23/3142 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49861 (2013.01); H01L 23/49866 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 2224/02319 (2013.01); H01L 2224/03436 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/11436 (2013.01); H01L 2224/13099 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/81191 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15747 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/207 (2013.01);
Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.


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