The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2019
Filed:
Apr. 02, 2018
Varian Semiconductor Equipment Associates, Inc., Gloucester, MA (US);
Min Gyu Sung, Essex, MA (US);
Naushad K. Variam, Marblehead, MA (US);
Sony Varghese, Manchester, MA (US);
Johannes Van Meer, Middleton, MA (US);
Jae Young Lee, Bedford, MA (US);
VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC., Gloucester, MA (US);
Abstract
Methods herein may include forming trenches in a stack of layers atop a substrate, and forming a gate dielectric within the trenches. Methods may further include forming a first work function (WF) metal atop the gate dielectric, and forming a capping layer over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches. The first WF metal may be removed from just a first trench of the trenches, and a second WF metal is then formed over the stack of layers, wherein the second WF metal is formed atop the gate dielectric within the first trench. An angled ion etch may then be performed to recess the gate dielectric and the second WF metal within the first trench, and to recess the gate dielectric and the first WF metal within a second trench. A gate metal may then be formed within the trenches.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile