The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2019
Filed:
Apr. 20, 2018
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Hemanth Jagannathan, Niskayuna, NY (US);
ChoongHyun Lee, Rensselaer, NY (US);
Richard G. Southwick, III, Halfmoon, NY (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06K 7/10 (2006.01); G06K 7/14 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/161 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
G06K 7/10574 (2013.01); G06K 7/1413 (2013.01); H01L 21/28238 (2013.01); H01L 21/28255 (2013.01); H01L 21/823807 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 29/161 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01);
Abstract
A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.