The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Oct. 08, 2018
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Kevin J. Anderson, Plano, TX (US);

Tarak A. Railkar, Plano, TX (US);

Walid M. Meliane, Frisco, TX (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 5/00 (2006.01); H01Q 9/04 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/185 (2013.01); H01Q 9/0407 (2013.01); H05K 1/021 (2013.01); H05K 1/181 (2013.01); H05K 5/0034 (2013.01);
Abstract

The present disclosure relates to a microelectronic package, which includes a base substrate, a perimeter wall, an electronic component, and a mold compound. The perimeter wall extends from a periphery of the base substrate to form a cavity that is over the base substrate and within the perimeter wall. The electronic component is mounted on the base substrate and exposed to the cavity. The electronic component is thermally coupled to a thermal management component, which extends through the base substrate and conducts heat generated from the electronic component. The electronic component is also electrically coupled to a wall signal via, which extends through the perimeter wall and transmits signals. The mold compound resides over the base substrate and within the cavity, so as to encapsulate the electronic component.


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