The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Mar. 05, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Michael Zierak, Colchester, VT (US);

Anthony K. Stamper, Williston, VT (US);

John J. Pekarik, Underhill, VT (US);

Vibhor Jain, Essex Junction, VT (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/764 (2013.01); H01L 21/76224 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01);
Abstract

Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.


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