The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Oct. 05, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Yukihiro Nagai, Saijo, JP;

Le-Tien Jung, Tainan, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/102 (2006.01); H01L 29/06 (2006.01); H01L 23/535 (2006.01); H01L 29/87 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1027 (2013.01); H01L 21/76224 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 29/0649 (2013.01); H01L 29/66378 (2013.01); H01L 29/66553 (2013.01); H01L 29/87 (2013.01);
Abstract

A semiconductor device includes: a substrate having a cell region and a peripheral region; a thyristor on the cell region; a MOS transistor on the peripheral region; a first shallow trench isolation (STI) between the thyristor and the MOS transistor; and a second STI between the first STI and the MOS transistor. The thyristor further includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region; patterned metal layers in the first semiconductor layer; vertical dielectric patterns on the patterned metal layers; and first contact plugs on the fourth semiconductor layer.


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