The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

May. 17, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Zhenxing Bi, Niskayuna, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Thamarai S. Devarajan, Albany, NY (US);

Balasubramanian Pranatharthiharan, Watervliet, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/02274 (2013.01); H01L 21/31111 (2013.01); H01L 21/76229 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 21/823412 (2013.01);
Abstract

A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.


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