The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Jul. 28, 2017
International Business Machines Corporation, Armonk, NY (US);
Devendra Sadana, Pleasantville, NY (US);
Dechao Guo, Niskayuna, NY (US);
Joel P. de Souza, Putnam Valley, NY (US);
Ruqiang Bao, Niskayuna, NY (US);
Stephen W. Bedell, Wappingers Falls, NY (US);
Shogo Mochizuki, Clifton Park, NY (US);
Gen Tsutsui, Glenmont, NY (US);
Hemanth Jagannathan, Niskayuna, NY (US);
Marinus Hopstaken, Carmel, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.