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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10381404 B1

PDFFull Text
Date of Patent:
Aug. 13, 2019

Filed:

Aug. 07, 2017

Integrated circuits with memory cells and methods for producing the same

Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Bhushan Bharat, Singapore, SG;

Juan Boon Tan, Singapore, SG;

Danny Pak-Chum Shum, Singapore, SG;

Yi Jiang, Singapore, SG;

Wanbing Yi, Singapore, SG;

Assignee:

GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;

Attorney:

Lorenz & Kopf, LLP

Primary Examiner:

Chuong A Luu

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/22 (2006.01); H01L 43/12 (2006.01); H01L 43/10 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); H01L 43/12 (2013.01); H01L 27/1203 (2013.01); H01L 43/02 (2013.01); H01L 43/10 (2013.01);
Abstract

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate having a buried insulator layer and an active layer overlying the buried insulator layer. A transistor overlies the buried insulator layer, and a memory cell underlies the buried insulator layer. As such, the memory cell and the transistor are on opposite sides of the buried insulator layer.

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Quick Actions:

Bharat, Bhushan. (2019). Integrated circuits with memory cells and methods for producing the same (U.S. Patent No. 10381404). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10381404

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