The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Sep. 17, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Chuan Hu, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3736 (2013.01); H01L 21/4871 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/01327 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/18162 (2013.01);
Abstract
Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.