The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Aug. 24, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Shinsuke Yada, Yokkaichi, JP;

Akihisa Sai, Yokkaichi, JP;

Kiyohiko Sakakibara, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); G11C 8/14 (2006.01); G11C 16/26 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/11521 (2017.01); H01L 27/11529 (2017.01); H01L 27/11551 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 21/30608 (2013.01); G11C 8/14 (2013.01); G11C 16/26 (2013.01); H01L 21/28 (2013.01); H01L 21/76802 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11521 (2013.01); H01L 27/11529 (2013.01); H01L 27/11551 (2013.01); H01L 27/11582 (2013.01);
Abstract

An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are replaced with, electrically conductive layers. An insulating cap layer is formed over the alternating stack. After formation of memory stack structures through each layer of the alternating stack and the insulating cap layer, a line trench straddling a neighboring pair of rows of the memory stack is formed. Sidewalls of the line trench include a sidewall of each memory stack structure within the neighboring pair of rows of the memory stack structures. A drain select gate dielectric and a drain select electrode line are formed within the line trench. The drain select electrode line controls flow of electrical current through an upper portion of a vertical semiconductor channel within each memory stack structure below the drain regions to activate or deactivate the neighboring rows.


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