The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Jan. 11, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Chang Wan Ha, San Ramon, CA (US);

Hang Tian, San Jose, CA (US);

Jong Kang, Pleasanton, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/324 (2019.01); G06F 1/3237 (2019.01); G06F 1/3234 (2019.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G06F 1/12 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 1/12 (2013.01); G06F 1/3237 (2013.01); G06F 1/3275 (2013.01); G06F 13/1673 (2013.01); G11C 7/1015 (2013.01); G11C 7/222 (2013.01); Y02B 70/12 (2013.01); Y02B 70/123 (2013.01); Y02B 70/126 (2013.01); Y02D 10/128 (2018.01); Y02D 10/13 (2018.01); Y02D 10/14 (2018.01);
Abstract

Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.


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