The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Nov. 20, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Jean-Pierre Colinge, Hsinchu, TW;

Cheng-Tung Lin, Hsinchu County, TW;

Kuo-Cheng Ching, Hsinchu County, TW;

Carlos H. Diaz, Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/41 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/775 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/16 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0676 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 29/16 (2013.01); H01L 29/413 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/7827 (2013.01); H01L 21/26586 (2013.01); H01L 29/66666 (2013.01);
Abstract

A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide.


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