The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2019
Filed:
Apr. 10, 2017
Applicant:
Sandisk Technologies Llc, Plano, TX (US);
Inventors:
Rahul Sharangpani, Fremont, CA (US);
Fumitaka Amano, Yokkaichi, JP;
Raghuveer S. Makala, Campbell, CA (US);
Fei Zhou, Milpitas, CA (US);
Keerti Shukla, Saratoga, CA (US);
Assignee:
SANDISK TECHNOLOGIES LLC, Addison, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11524 (2017.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/28282 (2013.01); H01L 21/76847 (2013.01); H01L 23/53266 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11582 (2013.01); H01L 29/7926 (2013.01);
Abstract
Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.