The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Apr. 24, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yun-Young Kim, Sejong-si, KR;

Pyoungwan Kim, Suwon-si, KR;

Hyunki Kim, Asan-si, KR;

Junwoo Park, Suwon-si, KR;

Sangsoo Kim, Cheonan-si, KR;

Seung Hwan Kim, Asan-si, KR;

Sung-Kyu Park, Cheonan-si, KR;

Insup Shin, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD, Samsong-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 25/11 (2006.01);
U.S. Cl.
CPC ...
H01L 25/117 (2013.01); H01L 21/561 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1076 (2013.01); H01L 2225/1082 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/18161 (2013.01);
Abstract

Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.


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