The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Aug. 10, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Chengjie Zuo, San Diego, CA (US);

Mario Francisco Velez, San Diego, CA (US);

Changhan Hobie Yun, San Diego, CA (US);

David Francis Berdy, San Diego, CA (US);

Daeik Daniel Kim, Del Mar, CA (US);

Jonghae Kim, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/15 (2006.01); H01L 23/31 (2006.01); H01L 23/14 (2006.01); H01L 23/00 (2006.01); H05K 1/02 (2006.01); H01L 23/64 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49805 (2013.01); H01L 21/4846 (2013.01); H01L 21/56 (2013.01); H01L 23/145 (2013.01); H01L 23/15 (2013.01); H01L 23/3121 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/02 (2013.01); H05K 1/0218 (2013.01); H01L 23/645 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10719 (2013.01);
Abstract

A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.


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