The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2019
Filed:
Aug. 14, 2017
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Amin Farshidi, Austin, TX (US);
Thomas Andrew Newton, Great Cambourne, GB;
Zhuo Li, Austin, TX (US);
Charles Jay Alpert, Cedar Park, TX (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 1/324 (2013.01); G06F 1/3296 (2013.01);
Abstract
Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.