The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Oct. 31, 2017
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Kun-Huang Yu, New Taipei, TW;

Shih-Yin Hsiao, Chiayi County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 49/02 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 28/00 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/4966 (2013.01);
Abstract

A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.


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