The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Mar. 14, 2017
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Wei Jiang, Hsinchu, TW;

Jia-Rong Chiou, Zhubei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11548 (2017.01); H01L 21/768 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11548 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76889 (2013.01); H01L 27/11556 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);
Abstract

A three-dimensional (3D) semiconductor device is provided, comprising a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer; and multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer in each of the sub-stacks.


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