The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2019
Filed:
Nov. 14, 2017
Applicant:
Stmicroelectronics, Inc., Coppell, TX (US);
Inventors:
Nicolas Loubet, Guilderland, NY (US);
Prasanna Khare, Schenectady, NY (US);
Qing Liu, Irvine, CA (US);
Assignee:
STMICROELECTRONICS, INC., Coppell, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01);
Abstract
A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.