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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10332911 B1

PDFFull Text
Date of Patent:
Jun. 25, 2019

Filed:

Dec. 15, 2016

Integrated circuits (ics) on a glass substrate

Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Shiqun Gu, San Diego, CA (US);

Daeik Daniel Kim, Del Mar, CA (US);

Matthew Michael Nowak, San Diego, CA (US);

Jonghae Kim, San Diego, CA (US);

Changhan Hobie Yun, San Diego, CA (US);

Je-Hsiung Jeffrey Lan, San Diego, CA (US);

David Francis Berdy, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:

Qualcomm Incorporated-Toler

Primary Examiner:

Farun Lu

Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 23/66 (2006.01); H01L 27/12 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/76251 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 21/823481 (2013.01); H01L 21/84 (2013.01); H01L 23/49894 (2013.01); H01L 23/528 (2013.01); H01L 23/66 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/1207 (2013.01); H01L 27/1222 (2013.01); H01L 27/1248 (2013.01); H01L 27/1266 (2013.01); H01L 29/1087 (2013.01); H01L 27/1255 (2013.01); H01L 29/66772 (2013.01);
Abstract

An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

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