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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10332599 B1

PDFFull Text
Date of Patent:
Jun. 25, 2019

Filed:

Mar. 12, 2018

Bias scheme for word programming in non-volatile memory and inhibit disturb reduction

Applicant:

Longitude Flash Memory Solutions Ltd, Dublin, IE;

Inventors:

Gary Menezes, San Jose, CA (US);

Krishnaswamy Ramkumar, San Jose, CA (US);

Ali Keshavarzi, Los Altos, CA (US);

Venkatraman Prabhakar, Pleasanton, CA (US);

Assignee:

LONGITUDE FLASH MEMORY SOLUTIONS LTD., Dublin, IE;

Attorney:

Kunzler Bean & Adamson

Primary Examiner:

Tri M Hoang

Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); H01L 29/167 (2006.01); H01L 29/36 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/08 (2006.01); H01L 27/11 (2006.01); H01L 27/1157 (2017.01); H01L 29/10 (2006.01); H01L 29/792 (2006.01); H01L 27/11524 (2017.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
G11C 16/107 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/36 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01); H01L 29/7923 (2013.01); G11C 16/0408 (2013.01); H01L 27/11524 (2013.01); H01L 29/7883 (2013.01);
Abstract

A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.

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