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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10326023 B1

PDFFull Text
Date of Patent:
Jun. 18, 2019

Filed:

May. 07, 2018

Semiconductor device including fin structure with two channel layers and manufacturing method thereof

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tung Ying Lee, Hsinchu, TW;

Chien-Chang Su, Kaohsiung, TW;

Wang-Chun Huang, Hsinchu, TW;

Yasutoshi Okuno, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Thinh T Nguyen

Int. Cl.
CPC ...
H01L 29/165 (2006.01); H01L 21/306 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 27/146 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/0217 (2013.01); H01L 21/02532 (2013.01); H01L 21/30625 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/0262 (2013.01); H01L 27/1461 (2013.01); H01L 29/267 (2013.01); H01L 29/6681 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.

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