The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Sep. 26, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Robert H. Dennard, Croton-on-Hudson, NY (US);

Bruce B. Doris, Slingerlands, NY (US);

Terence B. Hook, Jericho, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/283 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7833 (2013.01); H01L 21/283 (2013.01); H01L 21/7624 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/66621 (2013.01); H01L 29/7834 (2013.01);
Abstract

A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.


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