The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Apr. 07, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sivakumar Radhakrishnan, Portland, OR (US);
Mahesh S. Natu, Sunnyvale, CA (US);
Zhenyu Zhu, Folsom, CA (US);
Malay Trivedi, Chandler, AZ (US);
Randall L. Albion, Portland, OR (US);
Chris Ruffin, Chapin, SC (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/24 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 3/061 (2013.01); G06F 3/0631 (2013.01); G06F 3/0679 (2013.01); G06F 13/24 (2013.01); G06F 13/4068 (2013.01);
Abstract
Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.