The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Oct. 15, 2018
Globalfoundries Inc., Grand Cayman, KY;
Hongliang Shen, Ballston Lake, NY (US);
Erfeng Ding, Dresden, DE;
Guoxiang Ning, Clifton Park, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.