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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10319896 B1

PDFFull Text
Expired
Date of Patent:
Jun. 11, 2019

Filed:

Jun. 29, 2017

Shielded interconnects

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Javier A. Falcon, Chandler, AZ (US);

Adel A. Elsherbini, Chandler, AZ (US);

Johanna M. Swan, Scottsdale, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Ye Seul Nam, Chandler, AZ (US);

James S. Clarke, Portland, OR (US);

Jeanette M. Roberts, North Plains, OR (US);

Roman Caudillo, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Patent Capital Group

Primary Examiner:

Fernando L Toledo

Assistant Examiner:

Aaron J Gray

Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 31/0256 (2006.01); H01L 39/22 (2006.01); H01R 3/00 (2006.01); H05K 1/00 (2006.01); H05K 9/00 (2006.01); H01L 39/04 (2006.01); H01L 25/16 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01L 23/552 (2006.01); H01L 39/02 (2006.01); H01L 39/24 (2006.01); H01P 3/08 (2006.01); H01P 11/00 (2006.01); H05K 1/02 (2006.01); G06N 99/00 (2019.01); G06N 10/00 (2019.01);
U.S. Cl.
CPC ...
H01L 39/045 (2013.01); G06N 10/00 (2019.01); G06N 99/002 (2013.01); H01L 23/5386 (2013.01); H01L 23/5387 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 25/16 (2013.01); H01L 39/025 (2013.01); H01L 39/223 (2013.01); H01L 39/2493 (2013.01); H01P 3/081 (2013.01); H01P 11/003 (2013.01); H05K 1/0216 (2013.01); H01L 2223/6627 (2013.01);
Abstract

Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.

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