The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Jan. 30, 2018
Applicant:

Indian Institute of Science, Bangalore, Karnataka, IN;

Inventors:

Mayank Shrivastava, Bangalore, IN;

Milova Paul, Bangalore, IN;

Christian Russ, Diedorf, DE;

Harald Gossner, Riemerling, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/74 (2006.01); H01L 29/861 (2006.01); H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 29/735 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 27/0248 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/42356 (2013.01); H01L 29/7436 (2013.01); H01L 29/861 (2013.01); H01L 29/8613 (2013.01); H01L 29/0657 (2013.01); H01L 29/735 (2013.01);
Abstract

The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.


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