The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Jun. 11, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chien-Kuo Su, Luzhu Township, TW;

Cheng Hung Lee, Hsinchu, TW;

Chiting Cheng, Taichung, TW;

Hung-Jen Liao, Hsinchu, TW;

Jonathan Tsung-Yung Chang, Hsinchu, TW;

Yen-Huei Chen, Jhudong Township, TW;

Pankaj Aggarwal, Zhudong Township, TW;

Jhon Jhy Liaw, Zhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/227 (2013.01); G11C 11/419 (2013.01);
Abstract

A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.


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