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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10312229 B1

PDFFull Text
Date of Patent:
Jun. 04, 2019

Filed:

Oct. 20, 2017

Memory cells including vertical nanowire transistors

Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Victor Moroz, Saratoga, CA (US);

Jamil Kawa, Campbell, CA (US);

Thu Nguyen, San Jose, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:

Haynes Beffel & Wolfeld LLP

Yiding Wu

Primary Examiner:

Thao P Le

Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/11 (2006.01); G06F 17/50 (2006.01); H01L 29/786 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 17/5072 (2013.01); H01L 23/535 (2013.01); H01L 27/1104 (2013.01); H01L 27/1108 (2013.01); H01L 29/0676 (2013.01); H01L 29/4238 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H01L 21/823885 (2013.01); H01L 27/0688 (2013.01);
Abstract

A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.

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