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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10304840 B1

PDFFull Text
Date of Patent:
May. 28, 2019

Filed:

Mar. 30, 2016

Semiconductor device having stressor and method of manufacturing the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Keun-hee Bai, Suwon-si, KR;

Myeong-cheol Kim, Suwon-si, KR;

Kwan-heum Lee, Suwon-si, KR;

Do-hyoung Kim, Hwaseong-si, KR;

Jin-wook Lee, Seoul, KR;

Seung-mo Ha, Seoul, KR;

Dong-Hoon Khang, Daegu, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:

Lee & Morse P.C.

Primary Examiner:

Asok K Sarkar

Assistant Examiner:

Grant S Withers

Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/1116 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H01L 21/823425 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01);
Abstract

A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

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