The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2019
Filed:
May. 05, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Jaideep Mukherjee, San Jose, CA (US);
Saibal Saha, San Jose, CA (US);
Jianyu Li, Beijing, CN;
Yishan Wang, Beijing, CN;
Walter J. Ghijsen, San Jose, CA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A method for simulating an integrated circuit design is provided. The method includes executing a characterization tool over a first portion of a parameter space of a circuit design to form a netlist associated with the first portion of the parameter space. The method also includes forming a first sub-netlist from the netlist, selecting, for the first sub-netlist, a condition from at least one of a process, a voltage, or a temperature condition, and at least one parameter from the first portion of the parameter space. The method further includes executing a simulation of the first sub-netlist in a selected solver mode using the condition and the at least one parameter, and incorporating a result of the simulation in a circuit performance report, wherein the result is associated with the condition, with the at least one parameter, and with the first sub-netlist.