The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Mar. 05, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Michael G. Miller, Boise, ID (US);

Ashutosh Malshe, Fremont, CA (US);

Violante Moschiano, Avezzano, IT;

Peter Feeley, Boise, ID (US);

Gary F. Besinga, Boise, ID (US);

Sampath K. Ratnam, Boise, ID (US);

Walter Di-Francesco, Silvi, IT;

Renato C. Padilla, Jr., Boise, ID (US);

Yun Li, San Jose, CA (US);

Kishore Kumar Muchherla, Fremont, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/50 (2006.01); G06F 11/07 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/073 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/079 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01);
Abstract

Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.


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