The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Feb. 06, 2017
Applicant:

Netspeed Systems, Inc., San Jose, CA (US);

Inventors:

Pier Giorgio Raponi, San Jose, CA (US);

Sailesh Kumar, San Jose, CA (US);

Nishant Rao, San Jose, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/721 (2013.01); H04L 12/933 (2013.01); G06N 99/00 (2019.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
H04L 45/12 (2013.01); H04L 45/38 (2013.01); H04L 49/109 (2013.01); G06N 20/00 (2019.01); G06N 99/005 (2013.01);
Abstract

Example implementations described herein are directed to systems and methods for generating a Network on Chip (NoC), which can involve determining a plurality of traffic flows from a NoC specification; grouping the plurality of traffic flows into a plurality of groups; utilizing a first machine learning algorithm to determine a sorting order on each of the plurality of groups of traffic flows; generating a list of traffic flows for NoC construction from the plurality of groups of traffic flows based on the sorting order; utilizing a second machine learning algorithm to select one or more mapping algorithms for each group of the plurality of groups of traffic flows for NoC construction; and generating the NoC based on a mapping from the selection of the one or more mapping algorithms.


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