The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Sep. 14, 2012
Applicants:

Takao Akaogi, Cupertino, CA (US);

Yider Wu, Chu-Pei, TW;

Yi-hsiu Chen, Chu-Pei, TW;

Inventors:

Takao Akaogi, Cupertino, CA (US);

Yider Wu, Chu-Pei, TW;

Yi-Hsiu Chen, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11565 (2017.01); H01L 21/762 (2006.01); H01L 27/11568 (2017.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11565 (2013.01); H01L 21/76229 (2013.01); H01L 21/823425 (2013.01); H01L 21/823481 (2013.01); H01L 27/11568 (2013.01);
Abstract

A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.


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