The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Jun. 29, 2018
Applicant:

Niko Semiconductor Co., Ltd., New Taipei, TW;

Inventor:

Chih-Cheng Hsieh, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/373 (2006.01); H01L 21/52 (2006.01); H01L 23/36 (2006.01); H02P 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/52 (2013.01); H01L 23/36 (2013.01); H01L 23/3735 (2013.01); H01L 23/49811 (2013.01); H01L 23/49844 (2013.01); H01L 23/5385 (2013.01); H02P 27/06 (2013.01);
Abstract

A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.


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