The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Sep. 08, 2016
Applicants:

Qualcomm Technologies, Inc., San Diego, CA (US);

Yonsei University, University-industry Foundation, Seoul, KR;

Inventors:

Stanley Seungchul Song, San Diego, CA (US);

Seong-Ook Jung, Seoul, KR;

Hanwool Jeong, Seoul, KR;

Tae Woo Oh, Seoul, KR;

Giridhar Nallapati, San Diego, CA (US);

Periannan Chidambaram, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03K 3/356 (2006.01); H03K 19/096 (2006.01); H03K 3/037 (2006.01); H03K 3/012 (2006.01); H03K 3/017 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356104 (2013.01); H03K 3/012 (2013.01); H03K 3/017 (2013.01); H03K 3/037 (2013.01); H03K 3/0375 (2013.01); H03K 19/0963 (2013.01);
Abstract

Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.


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