The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Nov. 27, 2017
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Goran Mihajlovic, San Jose, CA (US);

Neil Smith, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/16 (2006.01); H01L 43/08 (2006.01); H01L 43/06 (2006.01); H01L 43/04 (2006.01); H01L 43/10 (2006.01); G11C 11/18 (2006.01);
U.S. Cl.
CPC ...
G11C 11/161 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); H01L 43/04 (2013.01); H01L 43/065 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01);
Abstract

A method and apparatus for deterministically switching a free layer in a spin orbit torque magnetoresistive random access memory (SOT-MRAM) cell is disclosed herein. In one embodiment, an SOT-MRAM memory cell is provided. The SOT-MRAM memory cell includes a magnetic tunnel junction, a ferromagnetic bias layer, and an antiferromagnetic layer. The magnetic tunnel junction includes a free layer having primarily two bi-stable magnetization directions, a reference layer having a fixed magnetization direction, and an insulating tunnel barrier layer positioned between the free layer and the reference layer. The ferromagnetic bias layer is configured to provide spin orbit torque via anomalous Hall effect and simultaneously configured to provide a magnetic bias field on the free layer to achieve deterministic switching. The antiferromagnetic layer is positioned below the ferromagnetic bias layer and is configured to pin a magnetization direction of the ferromagnetic bias layer in a predetermined direction.


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