The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10283418 B1

PDF
Full Text
Expired
Date of Patent:
May. 07, 2019

Filed:

Jul. 05, 2018
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Stmicroelectronics, Inc., Coppell, TX (US);

Inventors:

Hong He, Schenectady, NY (US);

James Kuss, Guilderland, NY (US);

Nicolas Loubet, Hudson, NY (US);

Junli Wang, Singerlands, NY (US);

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 21/845 (2013.01); H01L 21/0217 (2013.01); H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 21/823864 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/161 (2013.01);
Abstract

A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.


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He, Hong. (2019). Method of forming silicon germanium and silicon fins on oxide from bulk wafer (U.S. Patent No. 10283418). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10283418

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