The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2019
Filed:
Aug. 08, 2017
Intel Corporation, Santa Clara, CA (US);
Bryan L. Spry, Portland, OR (US);
Marcus W. Song, Battle Ground, WA (US);
Deepak M. Rangaraj, Hillsboro, OR (US);
Avinash N. Ananthakrishnan, Portland, OR (US);
Robert J. Hayes, Portland, OR (US);
Aimee D. Wood, Portland, OR (US);
Adam E. Letendre, Hillsboro, OR (US);
Brent R. Boswell, Aloha, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.