The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Feb. 25, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun Hsiung Tsai, Hsinchu County, TW;

Chien-Tai Chan, Hsinchu, TW;

Kuo-Feng Yu, Hsinchu County, TW;

Kei-Wei Chen, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7833 (2013.01); H01L 21/30608 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.


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