The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Sep. 28, 2017
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Tek Po Rinus Lee, Malta, NY (US);
Jinping Liu, Ballston lake, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/40 (2006.01); H01L 29/47 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/285 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/47 (2013.01); H01L 21/266 (2013.01); H01L 21/26506 (2013.01); H01L 21/28518 (2013.01); H01L 21/28525 (2013.01); H01L 21/76814 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H01L 29/401 (2013.01); H01L 29/78 (2013.01);
Abstract
Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include a semiconductor substrate having an n-FET region and a p-FET region each having source/drain regions; a titanium silicon (Ti—Si) intermix phase Ti liner on an upper surface of the n-FET region source/drain regions; and titanium silicide (TiSi) forming an upper surface of the p-FET region source/drain regions.