The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Sep. 18, 2017
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 21/76843 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53266 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05016 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/1145 (2013.01); H01L 2224/11452 (2013.01); H01L 2224/11614 (2013.01); H01L 2224/11845 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13017 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/2762 (2013.01); H01L 2224/27614 (2013.01); H01L 2224/27831 (2013.01); H01L 2224/73104 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/20106 (2013.01);
Abstract
A semiconductor device includes: a conductive structure, a conductive bump extending into the conductive structure and contacting the conductive structure along a first surface, the conductive bump configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface than the second surface.